What is FISC
FISC, which stands for Flexible Instruction Set Computer, is a set of multiple computer architectures with a main focus around the CPU - Central Processing Unit architecture design.
The final goal of this project is to subsequently create a classical computational system including Memory and I/O which can be used in multiple environments and implementations, such as FPGAs, ASICs and Virtual Machines.
The GitHub page for the complete project can be found here: github.com/FISC-Project
Important: The project is still under development.
How is the project organised
FISC can be more accurately described as a collection of multiple projects rather than a single project.
It essentially comprises the entire environment and ecosystem being designed for the CPU.
This means an execution environment was required to be developed in addition to the CPU. In other words, FISC is the combination of the design of the Instruction Set, Microarchitecture and the tools being created for it such as an LLVM C compiler, assembler, disassembler, debugger and of course a Virtual Machine developed both in VHDL and C++.
Motivations
This achievement was developed for a multitude of reasons.
The main motive was due to my personal need of developing a computer of my own. The desire of creating a machine that is close to what can be called a Turing Machine, is what truly motivated me to choose this project.
The secondary reason was due to the fact that this project is actually a final year singleton project that is being developed for the University of South Wales, in which I am taking the course of MEng. Computer Systems Engineering.
The final reason was to experiment by introducing a new kind of CPU architecture that comes close to the modern ARM and Intel architectures. This was done by combining some of the best features of both RISC and CISC worlds.
The name
As a soon to be engineer and programmer, it is common knowledge that we are perhaps one of the worst at naming things. FISC was named due to the fact that the CPU architecture is influenced by both ARM (RISC) and Intel (CISC).
Since this design shares some features of both worlds, the CPU was named FISC - Flexible Instruction Set Computer.
A more appropriate name would be appreciated if you happen to have a creative mind.
About me
The first iteration of this project develops a very simple R/CISC architecture and yet powerful design. In this first version, some of the specifications (both ISA and Microarch specs) can be found on the following table.
| Specification name | Description |
|---|---|
| Architecture type | RISC with CISC features (mostly RISC) |
| Datapath width | 64 bits |
| Core count | Single core (1 core) |
| Computing model | Von Neumann |
| Scalar and Vectorized (SISD on General purpose registers + SIMD on FPU) | |
| In order execution | |
| Stack + Register-Register + Register-Memory Machine | |
| Thread count | 1 thread |
| Pipeline depth | 5 stages (IF/ID/EX/MEM/WB) |
| Pipeline schedule | Static In-Order Single issue |
| Decode mechanism | Microcoded (CISC feature) |
| Register count | 32 GPR (General Purpose Registers); 13 SCR (Special Control Registers); Each register is 64-bits with some exceptions on the SCR |
| Branch Prediction support | No |
| Prefetching and Predecoding support | No |
| Cache count | L1 only (this will vary in the future) |
| L1 Instruction Cache size | 2KiB (subject to change) |
| L1 Instruction Size properties | Set Associative, 2 Way, 32 Sets, 32 byte data block (2 x 32 x 32 = 2048 bytes = 2 KiB) |
| L1 Data Cache size | 2 KiB (subject to change) |
| L1 Data Cache properties | Set Associative, 2 Way, 32 Sets, 32 byte data block (2 x 32 x 32 = 2048 bytes = 2 KiB) |
| Virtual Memory support | Yes |
| Virtual Memory TLB Cache size | TO DETERMINE |
| Floating Point Unit support | Yes |
| Interrupts and Exceptions support | Yes |
| Instruction count | 112 (including pseudo-instructions) |
| Arithmetic and Logic | |
| Branching | |
| Load and Store | |
| FPU | |
| CPU Status Control | |
| Interrupts | |
| Virtual Memory |
You can email me at: santosmiguel25@gmail.com
You can also get in touch on GitHub: github.com/miguelangelo78
And LinkedIn: linkedin.com/in/miguelacs
